1. Field of the Invention
This invention relates to a direct sequence (DS) spread spectrum (SS) communication receiver, and in particular to a method for acquisition of slot timing during initial cell search synchronization.
2. Description of the Related Arts
When power is applied to a mobile station the task of synchronization with a base station is initiated. This task is called “initial cell search.” The characteristics of the Universal Mobile Telecommunications System (UMTS) and the procedure for initial cell search to which the following description relates is described in the European Telecommunications Standards Institute (ETSI) publication TR 101 146 version 3.0.0, “Universal Mobile Telecommunications System, Concept evaluation.” As will be clear to those skilled in the art the instant invention is not restricted to use with the UMTS and may also be applied to other WCDMA (wide-band code division multiple access) systems. Reference is made to U.S. Pat. No. 5,982,809 to Liu which forms part of the prior art.
The initial cell search by the mobile station is performed in three steps and the first step is the acquisition of slot synchronization to the transmissions of the base station providing, through a fading path, the strongest signal at the receiver of the mobile station. With reference to FIG. 1 which is a schematic illustration of base station broadcast transmissions, base station transmissions are represented at 1, the transmission channel at 2, and the mobile station receiver at 3. In FIG. 1, by way of example, the transmissions from only two base stations BTS1 and BTS2 are shown.
These base station transmissions are not synchronized with each other and are maintained to transmit over common fixed duration time intervals referred to as slots and common fixed duration framing intervals referred to as frames. One frame comprises 15 slots. In FIG. 1, the start of a slot for the transmissions from base station BTS2 is shown delayed from the start of a slot for the transmissions from base station BTS1 by an arbitrary amount ‘t’ seconds.
The base station transmissions include a synchronization channel (SCH) aligned with the slot boundary and a primary common control physical channel (PCCPCH). The synchronization channel comprises a primary synchronization code (PSC) and a secondary synchronization code (SSC) as illustrated in FIG. 2. In FIG. 2, the primary synchronization code for each slot is represented as Cp, the secondary synchronization codes for respective slots are represented as Csi,0 to Csi,14. The code transmitted as the primary synchronization code (Cp) is repeated at the beginning of each slot by all base stations.
The BTS transmissions to the receiver 3 will be affected by channel 2. In FIG. 1, the transmissions of base station BTS2 are illustrated as received through a 3-path (multipath) channel 22 while the transmissions of base station BTS1 are illustrated as received through a 2-path channel 21. The signals from base stations BTS1 and BTS2 are effectively summed in channel 2 before arriving at receiver 3 as represented by “Σ” in FIG. 1. Correlation of the received signal with the expected primary synchronization code which is stored in the receiver provides a number of correlation peaks. The peaks are detected by, for example, PAC matched filter 31. The highest peak detected corresponds to that base station of the network (the found base station) to which the receiver will synchronize.
The second step of initial cell search establishes frame synchronization and identifies the code group of the base station found in the first step. The third step of initial cell search determines the scrambling code assigned to the found base station.
A correlation process is performed sample-by-sample and over one slot. The number of shifts of the input data used is the product of the number of chips per slot and the oversampling rate (OSR). The results of the correlation process are averaged over a number of slots and the position of the sample with highest correlation power is selected as the slot boundary. The number of slots used in the averaging process is referred to as the averaging depth.
It is possible also to select and store the positions of the largest peaks from the number of peaks found in the first step. This information can then be used for the remaining two steps to determine the best slot-timing when one detected peak is selected but does not provide satisfactory results in the second and/or the third steps. In such a case, other peaks detected in the first step may be selected and used in the second and third steps.
Pipelining methods are known whereby different cell search steps operate on different parts of the received data (input blocks). The sizes of the input buffer required depends upon the averaging depth of the individual steps. For an averaging depth of one frame per step, the required buffer size is equal to one frame of data.
The provision of some sort of memory storage is germane to the cell search process. Satisfactory performance of the second and third steps depends upon satisfactory performance previously of the first and second steps. When using the same (or part of the same) data portion with all three steps and if averaging is applied to various steps the required memory size increases. Application of averaging to the first step is necessary due to the variations in channel conditions. In order to obtain a reliable slot-timing approximation, it would usually be necessary to implement averaging over a number of slots. Averaging may also be applied (over a number of frames) to the second and third steps.
To obtain the slot-timing, the minimum required input data length for the first step, corresponding to correlation of a single slot with the primary synchronization code (PSC) is [(CHIPS—PER—SLOT+CHIPS—PER—SYMBOL)×OSR−1]. The number of chips per time slot is expressed as CHIPS—PER—SLOT and the number of chips per symbol as CHIPS—PER—SYMBOL. As synchronization for the second step is based on a codeword which is transmitted over one frame, one frame of input data samples for the second step is envisaged. Similarly one frame of input data samples for the third step would accommodate the periodic transmission of the scrambling codes.
With all three steps operating on the same data block and assuming an averaging depth of 15 slots (i.e. 1 frame) for the first step, an input data buffer for the cell search process will need to store (38656×OSR−1) complex samples. For an OSR of 4 and using 8 bits per I (in-phase) and 8 bits per Q (quadrature) component of each input sample, the required buffer size will be found as 309246 bytes. The memory size would of course increase further if averaging depths of more than 1 frame were applied to second and/or third steps. A buffer size sufficient to accommodate at least 2 frames of data, i.e. 614400 bytes would be more likely.